I had a much longer introduction written up in my draft document of this but now looking back at it, it's a little unnecessary. To summarize my thoughts; in an attempt to provide some motivating direct applications of what I have learned in classes, I want to begin writing about some projects that directly apply the theory from class to something more tangible. Hopefully they can demonstrate real-world issues that one can run into when implementing these concepts for real. This is also a good excuse for me to refresh my memory on many of these topics and provide a good written reference to hold on to.
Any errors/things that are unclear are on me. Hopefully there aren't too many and I'm not saying anything too wrong. 🤷♂️
Part 1: Basic Buck Converter Theory
This is a quick crash course of DC-DC switching buck converters using my knowledge from EE113, Power Electronics, and EE128C, Feedback Control Systems. In my power electronics class, we went over the basics of the most common types of power converters. Hopefully this is a good refresher for me and lets me put theory into practice. [This write up is really mainly for me and kinda but doesn't really begin from the very basics; it also tries to follow a linear progression to the best of my abilities but there many subtopics that loop back on themselves.]
In this design example I want to go through the basics of a buck converter again and then apply some feedback/controls knowledge to making a converter that can deliver a set output for a varying range of inputs. This will also allow us to look at the transient response of the output of the regulator, from startup and changes on the input, to sudden changes to the output load. Everything I write will be from what I remember from EE113/my notes/the textbook Fundamentals of Power Electronics by Robert Erickson. I didn’t look at the textbook that much during class, but as I now reference it for this project it reads very clearly and is an excellent reference. If anything is unclear here, definitely take a look at that book.
Before we get started, since we are engineers and want to make something that will work to power something in real life, we need to have a target design. I've gone ahead and made up some reasonable parameters to work around:
Target specifications:
- Input voltage range: 6V to 12V
- Output voltage: 3.3V or 5V, depending on feedback resistors
- Output current: 1A
- Ripple specifications: ~50mVpp (1%)
- Start up time specs?
- Stepped load response time?
- PSRR
Basic Circuit Topology:
Ideal Operation:
Let’s start by analyzing an ideal converter in periodic steady state operation. Periodic steady state means that the system varies within a defined period, but from period to period the state is identical. We just need to know a few rules to get started:- The average voltage over a period across an inductor is 0. Why?
$$\begin{align*}
V &= L\frac{di}{dt}\\
\int_{<T>} V dt &= L \int_{<T>} di
\end{align*}$$
If it wasn’t, the current through the inductor would grow with each cycle, and we cannot be in periodic steady-state.
- The average current through a capacitor is 0. Why?
$$\begin{align*}
I &= C\frac{dv}{dt}\\
\int_{<T>} I dt &= L \int_{<T>} dv
\end{align*}$$
If it wasn’t, the voltage across the capacitor would grow with each cycle, and we cannot be in periodic steady-state.
With this knowledge, we can take the next step. We can divide the circuit into two phases: one where the switch is open, and one where the switch is closed. We’ll also assume for now that the output capacitor is large and there is no ripple at Vout, and the converter is operating in continuous conduction mode (CCM). The assumption of CCM is important because we assume the voltage across the inductor in both phases is about constant (and the inductor does not ever get to 0 current).
When it is closed, the voltage across the inductor is:
$$V_{in} - V_{out}$$
When it is open, the voltage across the inductor is:
$$- V_{out}$$
$$- V_{out}$$
Balancing the time voltage products, we get:
$$(V_{in} - V_{out}) DT -V_{out} (1-D)T = 0$$
$$\boxed{V_{out} = D V_{in}}$$
$$(V_{in} - V_{out}) DT -V_{out} (1-D)T = 0$$
$$\boxed{V_{out} = D V_{in}}$$
Looking at it another way, the capacitor and inductor effectively form a low pass filter; the circuit still “works” without them (or if the time constant of the filter is much smaller than the switching period) as we can see the average DC voltage at the output is just Vin x the fraction of time it is on, which is D Vin. The load most likely won’t like this though so we filter out as much of the high frequency content as possible to get only the average.
In the ideal case of constant conduction mode, the period of switching doesn’t matter in steady state (as long as it stays in CCM)! Only the duty cycle is important. Let’s take a look at what the transient simulation looks like in steady state with a switching frequency for 1MHz and some slightly arbitrary component values chosen to make sure we are in CCM:
 |
| MOSFET as switch and ideal diode. |
With a fixed duty-cycle of 0.5 and input voltage of 10V, we expect a 5V output.
Short of a special simulators like PLECS designed specifically for power electronics which can do better steady-state simulation, I've just gone ahead and run this schematic in LTSpice for 100us and looked at the last 10us:
[may update with other frequency plots in the future]
While not perfectly at 5V, it's close. If we use "infinite" capacitors and inductors we will see our perfect 5V output. Where does this ripple come from?
Part 2: Non-ideality
How does the output voltage fluctuate when switching? Usually we model the ripple as generally linear (almost everything is linear if you zoom in enough, good ol' LiNeArIzAtioN) since we assume that most of the time the time constant of this charging and discharging, or the time constant of the RLC network, is much greater than the switching frequency. We'll start with the current ripple in the inductor with the classic inductor equation:
$$V = L\frac{di}{dt}$$
We can find the slope of the current change, or the $\frac{di}{dt}$ using this equation. With V = 5V, we get $\frac{5\text{V}}{10\text{uH}} = 500\text{kA/s}$. In 0.5us, the on time, we get a total peak to peak current ripple of 0.25A. This is indeed what we see in simulation:
Small aside to discontinuous mode (DCM) operation since the discussion of ripple is important and leads to where the boundary of CCM/DCM mode is: In DCM, the average inductor current is below half the peak current. With a bit of algebra equating the inductor voltage-time products, we can first find the boundary of the DCM mode. We know the max peak to peak current ripple will be (Vout/L) * (1-D)T = (Vin * D * (1-D) * T / L). So the load current will be half this: (Vin * D * (1-D) * T / (2L)).
$$R > \frac{2L}{D(1-D)^2T}$$
$$R > \frac{2L}{D(1-D)^2T}$$
 | ||
| As the load current goes down, the ripple will eventually touch 0. |
In DCM, the converter’s output is (derivation in Erikson, [elaborate on Kcrit]):
$$\begin{align*}
\frac{V_{out}}{V_{in}} &= \frac{2}{1+\sqrt{1+\frac{4K}{D^2}}}\\
K &= \frac{2L}{RT}, K < K_{crit}
\end{align*}$$
$$\begin{align*}
\frac{V_{out}}{V_{in}} &= \frac{2}{1+\sqrt{1+\frac{4K}{D^2}}}\\
K &= \frac{2L}{RT}, K < K_{crit}
\end{align*}$$
We can also now find the steady-state voltage ripple. With a 5V output and 5 ohm load, we get an average of 1A through the load. Assuming 1A goes into the load, the 0.25A/2 = 0.125A ripple up and down will be through the capacitor. This is not entirely true as the current going in and out of the capacitor will change the voltage so the current in the load will also change, but this is a good enough assumption for a back of the envelope calculation. Integrating the triangular waveform (just using area of triangle formula) of current, we get:
$$\begin{align*}
I &= C \frac{dv}{dt}\\
V &= \frac{1}{C} \int I dt\\
&= (0.5)(0.5us)(0.125A) / 1uF = 31mV
\end{align*}$$
I &= C \frac{dv}{dt}\\
V &= \frac{1}{C} \int I dt\\
&= (0.5)(0.5us)(0.125A) / 1uF = 31mV
\end{align*}$$
We see slightly less ripple, which is expected, and it is quite close.
Lossy Components:
I’ll be mainly focusing on the MOSFET and diode losses. The MOSFET can be modeled as a switch with a Rds on resistance, and some power dissipation in charging and discharging the gate. With this non-synchronous design the diode handles the second phase conduction, but will have a power dissipation around the forward voltage * the output load current. With synchronous converters this is replaced with another MOSFET which can have a low Rds on.
We’ll say for now the Rds on is 10mOhms, the switch is toggled with hard switching (MOSFET does not stay in the saturation region for long) and the diode has a voltage drop of 0.6V. Assuming we are delivering 5W to the load (5V, 1A), we can now calculate the losses in these two devices. For half the cycle, we have 1A going through the MOSFET.
$$(1\text{A})^2 * 10\text{mOhm} * 0.5 = \boxed{5\text{mW}}$$
We’ll say for now the Rds on is 10mOhms, the switch is toggled with hard switching (MOSFET does not stay in the saturation region for long) and the diode has a voltage drop of 0.6V. Assuming we are delivering 5W to the load (5V, 1A), we can now calculate the losses in these two devices. For half the cycle, we have 1A going through the MOSFET.
$$(1\text{A})^2 * 10\text{mOhm} * 0.5 = \boxed{5\text{mW}}$$
Of course, this is not really an accurate representation of the real losses in a MOSFET; losses during switching almost definitely dominate. This is also another problem with switching extremely fast; it’s difficult to quickly switch a large MOSFET on and off quickly. We’ll look at this more closely when we have real components and measure the losses in LTSpice.
For the other half of the cycle, we have 1A going through the diode.
$$(1\text{A}) * 0.6\text{V} * 0.5 = \boxed{0.6\text{W}}$$
These two alone will create an efficiency of approximately (5W) / (5W + 5mW + 0.6W) = 89% with most of the loss being in the diode.
This is where thermal modelling is also important to consider; if the diode is consistently dissipating 0.6W will it overheat? Will we need a heatsink? We’ll look at this more when considering real components.
Series resistance of inductors and capacitors will also cause further losses in the circuit but will also create more ripple on the output voltage. When we have some series resistance in the capacitor, the current going in and out will create a voltage drop across the resistor that is consistently alternating polarity and increase the ripple. Here’s a pictorial representation of what is going on:
 |
| The green and purple shaded regions are the current through the capacitor. |
Let’s take a look at what happens if we have 1 ohm of series resistance in the capacitor (excessive but chosen to make the change obvious)
Earlier we calculated that we had 0.125A either going into or out of the capacitor. With a 1 ohm resistor, we then expect a 0.125V deviation from 5V. Running the simulation, we get close to that, with a max of 5.11V and minimum of 4.90V. We can also see the maximums and minimums are where we expect: around the “zero crossings” of the ideal simulation.
Earlier we calculated that we had 0.125A either going into or out of the capacitor. With a 1 ohm resistor, we then expect a 0.125V deviation from 5V. Running the simulation, we get close to that, with a max of 5.11V and minimum of 4.90V. We can also see the maximums and minimums are where we expect: around the “zero crossings” of the ideal simulation.
Non-periodic steady-state:
Now how does this respond when not in periodic steady state? We’ve been skipping the start up of this regulator so far. Below is a plot showing the entire transient simulation of the ideal converter from the beginning. How can we model this ringing here, which looks characteristic of a second order system?
In fact if we just step the switch (turn on without any switching) and ignore the final output level, we get the same shape but just continuous:
Just looking at the RLC system on its own, we can write the classic second order transfer function from the input to the output:
$$\begin{align*}
\frac{V_{out}}{V_{in}} &= \frac{R || \frac{1}{j\omega C}}{(R || \frac{1}{j\omega C}) + j\omega L}\\
R || \frac{1}{j\omega C} &= \frac{\frac{R}{j\omega C}}{R + \frac{1}{j\omega C}} = \frac{R}{1 + j\omega RC}\\
\frac{V_{out}}{V_{in}} &= \frac{\frac{R}{1 + j\omega RC}}{\frac{R}{1 + j\omega RC} + j\omega L}\\
&= \frac{R}{R + j\omega L + (j\omega)^2RLC}\\
&= \frac{1}{1 + j\omega \frac{L}{R} + (j\omega)^2LC}\\
&= \frac{\frac{1}{LC}}{\frac{1}{LC} + s \frac{L}{R}\frac{1}{LC} + s^2}\\
&= \frac{w_n^2}{w_n^2 + 2\zeta w_n s + s^2}\\
&= \frac{1}{1 + j\omega \frac{1}{Q w_n} + (\frac{j\omega}{w_n})^2}\\
\end{align*}$$
\frac{V_{out}}{V_{in}} &= \frac{R || \frac{1}{j\omega C}}{(R || \frac{1}{j\omega C}) + j\omega L}\\
R || \frac{1}{j\omega C} &= \frac{\frac{R}{j\omega C}}{R + \frac{1}{j\omega C}} = \frac{R}{1 + j\omega RC}\\
\frac{V_{out}}{V_{in}} &= \frac{\frac{R}{1 + j\omega RC}}{\frac{R}{1 + j\omega RC} + j\omega L}\\
&= \frac{R}{R + j\omega L + (j\omega)^2RLC}\\
&= \frac{1}{1 + j\omega \frac{L}{R} + (j\omega)^2LC}\\
&= \frac{\frac{1}{LC}}{\frac{1}{LC} + s \frac{L}{R}\frac{1}{LC} + s^2}\\
&= \frac{w_n^2}{w_n^2 + 2\zeta w_n s + s^2}\\
&= \frac{1}{1 + j\omega \frac{1}{Q w_n} + (\frac{j\omega}{w_n})^2}\\
\end{align*}$$
$$w_n = \frac{1}{\sqrt{LC}}, \zeta = \frac{1}{2R}\sqrt{\frac{L}{C}}, Q = R\sqrt{\frac{C}{L}}$$
Plugging in values, we get:
$$f_n = 50.3kHz, \zeta = \frac{1}{2R}\sqrt{\frac{L}{C}} = 0.316$$
Using some more forumlas from EE128C, we can also calculate the percent overshoot:
$$\begin{align*}
OS &= e^{-\zeta \pi / \sqrt{1-\zeta^2}}\\
&= e^{-0.316 \pi / \sqrt{1-0.316^2}} = 35\%
\end{align*}$$
$$\begin{align*}
OS &= e^{-\zeta \pi / \sqrt{1-\zeta^2}}\\
&= e^{-0.316 \pi / \sqrt{1-0.316^2}} = 35\%
\end{align*}$$
Settling time to within 2% of the final value:
$$\begin{align*}
T_s &= \frac{4}{\zeta w_n}\\
&= \frac{4}{0.316(316krad/s)} = 40us
\end{align*}$$
$$\begin{align*}
T_s &= \frac{4}{\zeta w_n}\\
&= \frac{4}{0.316(316krad/s)} = 40us
\end{align*}$$
Now let's see what happens when we step the output current. I've gone ahead and changed the circuit to step the output from 0.1A to 1A and back with a different load resistor:
Whoa! We get a practically non-decaying oscillation at around 50kHz, the resonant frequency, which is not good. This makes sense as the current source has effectively infinite resistance, and replacing the constant load resistor with 10k has made the circuit nearly a perfect LC tank! The sharp step's frequency component at the resonant frequency as a result is amplified. This is not good.
Coming back to the stepped input; all the values match what we see in simulation. So why exactly do we see the nearly same response with or without switching?
Part 3: Small Signal Modeling
To do further analysis of this system in the time and frequency domain, we need to somehow abstract away the switching elements. Let’s put together a system-level block diagram of what this circuit is doing. We’ll also make a replacement of the switching block with an “averaged” model; Erickson has a nice derivation of this model and an LT application note linked below also covers this. With the assumption that the fluctuation per cycle due to switching is small, we can average the voltage and currents going through components over one switching cycle, and then consider the change in these averages. We can use the normal differential equations on these average signals. This means we can model frequency dependent effects but only at “low frequencies,” much lower than the switching frequency.
Averaging waveforms for the buck converter:
$$\begin{align*}
L\frac{d\langle i(t)\rangle_{T_s}}{dt} &= d(t)\langle v_{in}(t) - v_{out}(t)\rangle_{T_s} + d'(t)\langle - v_{out}(t) \rangle_{T_s}\\
C\frac{d\langle v(t)\rangle_{T_s}}{dt} &= \langle i(t) \rangle_{T_s} - \frac{\langle v(t)\rangle_{T_s}}{R}
\end{align*}$$
$$\begin{align*}
L\frac{d\langle i(t)\rangle_{T_s}}{dt} &= d(t)\langle v_{in}(t) - v_{out}(t)\rangle_{T_s} + d'(t)\langle - v_{out}(t) \rangle_{T_s}\\
C\frac{d\langle v(t)\rangle_{T_s}}{dt} &= \langle i(t) \rangle_{T_s} - \frac{\langle v(t)\rangle_{T_s}}{R}
\end{align*}$$
After averaging, we can also do the classical small signal analysis of linearizing around an operating point.
Each of the averages can be decomposed into a large signal and small signal superimposed on top, including the duty cycle signal. $\hat{d}$ means averaged, $d'$ means the opposite $(1-d)$. Here is the rather convoluted derivation of the small signal elements of the inductor in a buck converter:
$$\begin{align*}
L\frac{d(I_L + \hat{i}_L(t))}{dt} =& (D + \hat{d}(t))(V_{in} + v_{in}(t) - V_{out} - v_{out}(t)) + (D' - \hat{d}(t))(-V_{out} - v_{out}(t))\\
=& D(V_{in} -V_{out}) + \\
&\hat{d}(t)(V_{in} -V_{out}) + Dv_{in} - Dv_{out} + \\
&\hat{d}(t)(v_{in} - v_{out}) + \\
& D'(-V_{out}) +\\
& D'(-v_{out}) - \hat{d}(t)(-V_{out})+\\
& \hat{d}(t)(-v_{out}) \\
\approx& D(V_{in} -V_{out}) + D'(-V_{out}) +\\
&\hat{d}(t)(V_{in} -V_{out}) + Dv_{in} - Dv_{out} + D'(-v_{out}) + \hat{d}(t)(V_{out})\\
=& DV_{in} - V_{out} +\\
& Dv_{in} - v_{out} + \hat{d}(t)V_{in}
\end{align*}$$
$$\begin{align*}
L\frac{d(I_L + \hat{i}_L(t))}{dt} =& (D + \hat{d}(t))(V_{in} + v_{in}(t) - V_{out} - v_{out}(t)) + (D' - \hat{d}(t))(-V_{out} - v_{out}(t))\\
=& D(V_{in} -V_{out}) + \\
&\hat{d}(t)(V_{in} -V_{out}) + Dv_{in} - Dv_{out} + \\
&\hat{d}(t)(v_{in} - v_{out}) + \\
& D'(-V_{out}) +\\
& D'(-v_{out}) - \hat{d}(t)(-V_{out})+\\
& \hat{d}(t)(-v_{out}) \\
\approx& D(V_{in} -V_{out}) + D'(-V_{out}) +\\
&\hat{d}(t)(V_{in} -V_{out}) + Dv_{in} - Dv_{out} + D'(-v_{out}) + \hat{d}(t)(V_{out})\\
=& DV_{in} - V_{out} +\\
& Dv_{in} - v_{out} + \hat{d}(t)V_{in}
\end{align*}$$
And for the capacitor:
$$\begin{align*}
C\frac{d(V_{out} + \hat{v}_{out}(t))}{dt} =& I_L + i_l -\frac{V_{out} + v_{out}}{R}
\end{align*}$$
Below is a diagram showing all the "small signal" loops from these differential equations. Putting them all together we can see how perturbations on Vin or the duty cycle will affect the output.
We can now create a signal block diagram for the small signal analysis:
AC Response:
How can we simulate this in the AC domain? The switching element is not time invariant. We need to somehow capture this averaged circuit model into the switches. Using this SPICE model from [Erikson] for the transistor and diode, we can now capture the AC response in CCM and DCM. The derivation of this subcircuit is not derived here. (I may want to talk more about DCM mode in the future as it is fairly important.)
*CCM-DCM1
.subckt CCM-DCM1 1 2 3 4 5
+ params: L=10u fs=1e6
Et 1 2 value={(1-v(u))*v(3,4)/v(u)}
Gd 4 3 value={(1-v(u))*i(Et)/v(u)}
Ga 0 a value={MAX(i(Et),0)}
Va a b
Ra b 0 1k
Eu u 0 table {MAX(v(5),
+ v(5)*v(5)/(v(5)*v(5) + 2*L*fs*i(Va)/v(3,4)))} (0 0) (1 1)
.ends
.subckt CCM-DCM1 1 2 3 4 5
+ params: L=10u fs=1e6
Et 1 2 value={(1-v(u))*v(3,4)/v(u)}
Gd 4 3 value={(1-v(u))*i(Et)/v(u)}
Ga 0 a value={MAX(i(Et),0)}
Va a b
Ra b 0 1k
Eu u 0 table {MAX(v(5),
+ v(5)*v(5)/(v(5)*v(5) + 2*L*fs*i(Va)/v(3,4)))} (0 0) (1 1)
.ends
Simulating our previous transient simulations we can see that we get effectively the same response without the switching ripple.
 |
| The previous figure zoomed in at the end. |
Now we can also run AC simulations and see that we get out expected transfer functions:
We do get the 20dB of gain (or 10x) from the PWM to output, and get a -6dB (or 0.5x) from the input to the output at DC, and see the 2nd order resonant peak at ~50kHz.
Feedback:
How can we control this so we get faster settling of the output? How can we control the output voltage so that it is also independent of the input voltage? How can we make everything better (not really but it always seems like it)? Feedback! Currently this system has no feedback. If we can control the duty cycle of the PWM signal in response to the output voltage, we will have a complete buck converter.
From a circuit level it would look like this:
And its corresponding signal block diagram:
Now with feedback we can continue to use classical control theory to analyze the stability of the system and how to properly choose components/insert compensation for faster settling, greater stability, less steady-state error, etc.
Let's first consider the loop from the reference to the output, and then later the loop from vin to vout and iout to vout.
Let’s plot the bode plot of these transfer functions in theory first and then alongside what we see in simulation. From a stability standpoint, we’ll be using phase margin to evaluate the design. There are some other considerations with switching systems (e.g. the PWM modulator is like a sample and hold system which could potentially have drastic effects on stability) but for now we’ll assume the switching period is small relative to the frequencies we are looking at.
The first change we need to make to this circuit is to remove the loading resistor we have been using so far. Why? From our equations earlier we know the damping ratio is inversely related to the resistance of the load, and with our small 5 ohm resistor the damping of the system has been well controlled. However, when using the buck regulator with true loads, we cannot depend on it to be resistive. Many circuits these days with many digital and analog ICs look more like periodic current sources with a high input impedance. If we change the resistance to be 100kohms and keep the same L and C, we get a damping of 1.5e-5, or a Q of 31k! This will make output resonate. If we change the output capacitance to a more realistic 100uF, we get a Q that is even higher. We need our feedback to be able to keep the output stable despite large changes in the load resistance.
I’ve plotted some bode plots here in MATLAB (and will move them over to python at another time but MATLAB just makes feedback and stability analysis much easier with all its built in functions):
Here’s the transfer function of JUST the ideal output filter times the input voltage (Gvd) with a load resistance of 100k; this is effectively what the transfer function would look like with an ideal opamp with infinite bandwidth:
We can see the DC gain of 20dB (10V input) and a clear resonant peak.
Now if we put in the gain of the opamp and the scaling of the PWM modulator (I’m just going to assume the ramp scales to VDD) without any compensator/feedback, we get this:
The opamp is modeled as having a DC gain of 100k and a pole at 20Hz.
We can see that the output filter, over a wide range of load resistance values from 10 to 100k creates a rapid change in phase from 0 to -180 degrees since the Q is still relatively high. With this alone and no other non-idealities, our system will “always” be stable as we never cross -180 degrees but the phase margin will be very poor. Adding in the single pole of the opamp, we now easily have no phase margin anymore. We also need to make sure that our point where gain goes below 0dB is past the resonant frequency of the LC filter otherwise the regulator will definitely resonate. How can we make this happen despite having -270 degrees of phase after the resonant point? We need to add in a compensator! Specifically, our compensator will need to have (left hand plane) zeros before the resonant frequency to add back phase.
One thing for us to note is that we have been modeling our passives as ideal for now. If we add in 20mOhms of series resistance to the inductor and capacitor, we get an additional zeros (the derivation of the exact transfer function is really just an algebra exercise, refer to the TI document linked at the end for the full form) :
From here on out we will periodically check the effect of losses on our feedback system. As we can see from the graph above though, for a buck converter the losses here will improve our phase margin, so if we design with ideal components we should be fine with real components.
With these preliminary plots, how can we design our compensator to give us the phase boost we need for the phase margin? One zero will give us at most a 90 degree boost, which is not enough. We need two zeros to give us room for any phase margin. Let’s take a look at this classic design that wraps feedback around our opamp:
 |
| Classic Type-III Compensator (diagram from TI) |
Again, without going through all the algebra and just taking the expression from the linked TI document, the compensator’s transfer function takes on this form:
$$\begin{align*} H_{comp} &= \frac{A_{OL}(s)}{1+A_{OL}(s)\beta(s)}\\ \beta &= \frac{R_1R_3C_1s(s+\frac{C_1+C_2}{C_1C_2R_2})(s + \frac{1}{R_3C_3})}{(R_1+R_3)(s+\frac{1}{R_2C_2})(s+\frac{1}{(R_1+R_3)C_3})} \end{align*}$$
[Another quick detour]: the expression for the closed loop compensator as shown in TI isn’t exactly correct but is close enough for use. If we remember that for a general inverting amplifier we get a gain of $-\frac{Z_f}{Z_i}$ assuming the open loop gain is large. Where does this actually come from again? Remember, the feedback factor beta for an inverting amplifier is actually $\frac{Z_i}{Z_i+Z_f}$. There is an additional forward gain factor of $\frac{Z_f}{Z_i+Z_f}$. We write it all out we can see how the beta approximation can be made:
$$\begin{align*} \frac{Z_f}{Z_i+Z_f} \frac{A(s)}{1+A(s)\frac{Z_i}{Z_i+Z_f} } &= \frac{A(s)}{\frac{Z_i+Z_f}{Z_f} (1+A(s)\frac{Z_i}{Z_i+Z_f}) }\\ &= \frac{A(s)}{1 + \frac{Z_i}{Z_f}+A(s)\frac{Z_i}{Z_f}}\\ &= \frac{A(s)}{1 + (1+A(s))\frac{Z_i}{Z_f}}\\ &\approx \frac{A(s)}{1 + A(s)\frac{Z_i}{Z_f}}\end{align*}$$
The compensator’s total transfer function is now approximately 1/beta, which can be arranged as so:
$$ \frac{1}{\beta} = \frac{(1+\frac{s}{\omega_{z0}})(1+\frac{s}{\omega_{z1}})}{sR_1(C_1+C_2)(1+\frac{s}{\omega_{p0}})(1+\frac{s}{\omega_{p1}})}$$
Where along with the pole at the origin:
$$\omega_{z0} = \frac{1}{R_2C_2}, \omega_{z1} = \frac{1}{(R_1+R_3)C_3}, \omega_{p0} = \frac{C_1+C_2}{C_1C_2R_2}, \omega_{p1} = \frac{1}{R_3C_3}$$
Assuming that $C_1 << C_2$ and $R_3 << R_1$:
$$\omega_{z0} = \frac{1}{R_2C_2}, \omega_{z1} = \frac{1}{R_1C_3}, \omega_{p0} = \frac{1}{R_2C_1}, \omega_{p1} = \frac{1}{R_3C_3}$$
Here's the initial circuit I want to simulate:
I've chose some a basic jelly-bean opamp to get started with, the ____. (A heads up to anyone: when simulating in SPICE the solver did not like every opamp model I gave it. I didn't look too much into it and just moved to a different opamp.) I originally was going to choose the NE5532 but the input clamp might pose a problem.
[WIP; I have some other school work I should be working on instead :); will hopefully be working on this periodically. ]
Part 4: Final Design, Implementation, and Reality
This is the fun (and not fun) part of most projects: making the idea come to life! Let’s take a look at some design considerations:
PWM:
For the PWM generation we’re going with a classic triangle wave (instead of ramp) with a comparator. Here’s a quick circuit that generates that signal and the test bench in LTSpice:
The triangle wave is generated with a simple integrator circuit and square wave comparator/hysteresis circuit. When the comparator output is high, the triangle wave decreases until it trips the hysteresis point, at which point the output goes low and causes the triangle wave to increase.
We’ll be switching the regulator at 400kHz instead of 1MHz like we used in the very early simulations since we are building this out of discrete components, not on-chip. Parasitics, while we will try to mitigate as much as possible with good layout techniques, can be an issue and we need to be sure they do not significantly affect the performance of the regulator.
For the comparators, I’ll be using the LM393/LM2903. We want to use real comparators instead of op-amps as comparators because they will be faster in terms of slew rate and delay from the trip point to the output for the same cost.
To get the frequency in the ballpark, we can make some simple calculations. We’ll actually want to make a 200kHz triangle wave which generates 400kHz in ramps.
$$I = C \frac{dv}{dt}$$
$$\frac{dv}{dt} = \frac{I}{C}$$
$$V_{DD}/(1\text{s}/(2*200000)) = (V_{DD}/2)/(RC)$$
$$RC = \frac{1}{2}(2.5\text{us})$$
$$R = 4.7\text{k}$$
$$C = 266\text{pF}$$
I chose 4.7k and 200pF which should give 265kHz.
Switch:
For the switch I chose a PMOS so I would not have to deal with bootstrapping or charge pumping for a high-side NMOS. We want a PMOS with decent Rds,on without excessively large gate charge. This also means we need to invert the polarity of the control logic.
For the switch I chose a PMOS so I would not have to deal with bootstrapping or charge pumping for a high-side NMOS. We want a PMOS with decent Rds,on without excessively large gate charge. This also means we need to invert the polarity of the control logic.
To drive the gate quickly we will use a simple push-pull stage driver. When doing some research on what others have used for a gate driver that isn’t just an IC, I saw this style of design in a few of the entries of a buck converter competition on reddit. The only small downside is that it won’t be able to pull the output all the way to 0 due to the diode, but the diode is necessary so that the upper transistor can actually turn on.
Some experimentation with the gate driver in LTSpice shows some interesting behavior with difference BJTs. Changing between 2N3904 and 2N2222s shows drastically different turn off times. This is caused by the storage time of the BJTs. Decreasing the base current will improve this time at the cost of generally slower switching, and increasing this will only make turn off time worse. Below is a schematic showing four different drivers: the 2N3904, the 2N2222, adding a Baker clamp, and finally changing the bottom transistor to a jellybean MOSFET. The last two options are by the fastest.
With a MOSFET we don't need to worry about this storage time changing with the supply voltage (as the base current changes). The Baker clamp is neat as it effectively limits the base current by diverting some of it to the collector and reduces the storage time. I'll for now chose the MOSFET, but we'll need to re-simulate this with a proper model of the source that will drive this driver. It's possible we really don't need a driver, but this is a fun detour anyways.
Voltage Reference:
The voltage reference will be derived from a Zener diode and a constant current source. The current source is made from a simple set of back-to-back PNP transistors. The Zener diode’s voltage can be tuned by adjusting the current.
How does the current source work? The main current is set by R1. We know that when properly biased in forward active $V_{EB}$ will be about one diode drop of 0.6 to 0.7V (with “normal” currents). Then we know the current in the right branch is now $I = V_{EB,Q1}/R_1$. This will be effectively constant across a wide range of supply voltages because Q2 acts as a high impedance node looking into the collector. Q2 has negative feedback; if you try to draw more current the $V_{EB}$ of Q2 will decrease as the voltage drop across R1 increases and the current will have to decrease.
The complete circuit:
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| Output voltage from simulation. |
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| Input and output power (input is negative due to sign convention) |
Input and output power at 0.5A load current (81.2% efficient):
(Late March) All the parts and the PCB are here: time to solder it up:
Here comes the potentially not-fun part — testing. When it all works though things are great :) It did indeed not work on first power up. :(
At first it was trying to draw more than the current limit of 0.1A that I set (voltage at 10V); increasing the limit to 0.4A caused some smoke to come out of somewhere but I didn’t see which part. Turning off the supply and inspecting the parts, I saw no part that was visibly damaged. Eventually the setup settled to drawing about 41mA and the output was a steady ~1.68V (even when changing the input voltage). I desoldered the main FET just to see if the ramp generation alone was working. The ramp was not working and the output was still at around 1.68V. Replacing both ICs showed no change in behavior (and I didn’t expect the ICs to break given that they were powered off of the input voltage directly). However, I did not expect the output to have any voltage and suspect it must be powered through some protection diodes or something. The 5V voltage reference was working fine.
Doing some debugging, I found out why the ramp was not working: the comparator pull up resistance. I was trying to size a small resistor as the pull up so that it was negligible to the resistor going into the integrator and assumed the comparator’s output could easily sink a decent amount of current when pulling down. [It worked in SPICE didn’t it? :) ] When probing the output of the comparator for the triangle wave generation, I saw it was sitting around mid-rail despite the positive input being lower than the negative one. Looking at the datasheet gave me my answer as to why this was happening:
My 270 ohm resistor with its ~3.6V drop was causing a 13mA sink, which is right up where the saturation voltage goes way up. I’ll need to change that to like a 10k resistor so when pulling down fully at 10V there is only about 1mA flowing. This also means my integrator’s R should be an order of magnitude greater than that (4.7k to 100k), and the C will need to be another order of magnitude smaller to keep the same oscillation frequency (already 200p). Not good. That or I change to a different comparator with a push-pull output stage. (I was originally going to use a push-pull one; forgot why I decided to stick with the 393). I bought a few TS3702CDT which are pin compatible and has a nice CMOS push-pull output stage.
Huzzah! With the new comparator the triangle wave generation generally works (but is a little wack). The top side is clipping and causing the frequency to be lower than expected but I’ll fix that later. I'll need to see if the comparator is just really slow to switch high.
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| I apologize for the poor scope photos; I really should have saved the screen to a flash drive. |
(Now it's May...) But the buck converter is still not… bucking. Probing the switching MOSFET’s gate I see that nothing is happening despite the comparator for the PWM output having a high output. The MOSFET controlling the gate driver is doing nothing hmm…
I looked back at my KiCAD schematic and saw my error:
That should be a NPN MMBT3904. Doh! I must have made this error when I was swapping out my BJTs for the SMD version of those parts and just copied over the PNPs being used for the voltage reference. With a PNP transistor, when Q3’s gate is pulled high we get a huge current through the PNP through the base and the collector as we try to pull the base down to ground. This is what caused the smoke on my first power up and broke Q3!
I had through-hole versions of the 3904 available so after swapping that in and replacing the BSS123, I was hopeful that I would see 5V at the output. (I could replace the 3904 with a SMD one in the future as it is perfectly footprint and pin compatible.) Fingers crossed!
5V! It works! Here’s the start up transient with a 10V input:
I measured the performance under different load currents with an electronic load (83.8% at 0.5A):
Iout takes into account the current drawn by the indicator LED.
At 600mA the output voltage measured by the load started jumping around so I probed the output to be greeted with a rather large amount of ripple:
I decided to stop the load test here for now; if I used a resistor as the load I could probably continue as it would dampen and reduce the Q of the output filter.
Here’s the ripple at 300mA:
And finally the delay through the comparator from when the FB goes above the triangle wave and the output goes high (the cursors are around the pulse width but the actual delay looks like ~200ns):
I need to debug the triangle wave peak as that is affecting the performance of the regulator but for now I’m pretty happy that I got this working.
References:
Erickson, Robert W., and Dragan Maksimović. Fundamentals of Power Electronics. Norwell, Mass: Kluwer Academic, 2001.
Nise, Norman S. Control Systems Engineering. Hoboken, NJ: Wiley, 2004. Print.
Zhang, Henry J. Modeling and Loop Compensation Design of
Switching Mode Power Supplies. https://www.analog.com/media/en/technical-documentation/application-notes/an149fa.pdf, 2015.
https://www.ti.com/lit/an/slva301/slva301.pdf
https://www.ti.com/seclit/ml/slup384/slup384.pdf
https://www.onsemi.cn/pub/collateral/tnd352-d.pdf
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