iCE40 FPGA Tinkering

After my very short experience with getting the Vivado toolchain setup to use the the Pynq FPGA board a few years ago, I've decided to get back into doing some projects with a FPGA again. I only ever got around to blinking an LED before putting the board aside; I had no solid projects in mind to make. The only reason I tried using it was that I was able to get one for free and it is the board used in the digital design class at Berkeley. I know it is a very powerful device and has lots of nice peripherals directly on the board so I may come back to it in the future. (Most digital design time is really spent in simulation anyways so the exact hardware doesn't matter that much.)

But man, the complete Vivado toolchain is nearly 80GB installed, and the bloat of everything with respect to it did not sit nicely with me. So recently I set out to find a different FPGA with a nicer ecosystem. From other projects I've seen online the first one I looked into and eventually settled on was the Lattice series of iCE40 FPGAs. The configuration bitstream has been reverse-engineered and a series of open-source tools have been developed for using these iCE parts. Synthesis, place-and-route, and bitstream generation all can be done through some simple steps. (Most other FPGAs still have locked down bitstreams and is why you need to use vendor-specific tools to do the synthesis and place-and-route. Being tools that are developed by large corporations with lots of money, they may/probably have better outputs from these steps (e.g. more optimized synthesis, better place-and-route of logic cells for better timing, etc.).)

I picked up a UPduino board with its iCE40-UP5K FPGA and installed the APIO ecosystem for the development and build toolchain. APIO makes it super convenient to develop for these FPGAs as it bundles together all of the open source tools.

General setup process (so I don't forget it; recently I had to re-lookup how I setup my STM32 toolchain back in 2018 so if I wanted to use them for a real project I would be able to):

1. Install APIO
2. Generally followed this guide.
3. Initialize project with apio init --board iCE40-UP5K -s
1. -s allows us to customize the SConstruct file so that we can the build process look into subdirectories for the source files.
4. For simulation use apio sim
1. Simulates from *_tb.v files
5. apio build to build the verilog
6. For some reason apio upload would not work for me; I suspect there is a PATH problem with my python setup (error: 'WindowsPath' object is not iterable)
1. I just manually uploaded with iceprog -I A [path to bitstream]

Within minutes I had some blinky LEDs going current controlled by the internal LED peripheral, and running a simulation was relatively straightforward. Next steps are generating PWM and then maybe generating some VGA signals. Still not sure if this the best platform to be using but for small projects the simplicity is nice.

Aside: Some time ago I had did about a day's worth of tinkering with Verilog and getting simulation setup with iverilog and gtkwave after reading blog posts on zipcpu and gaining some interest in HDL again. Getting everything setup on Windows is slightly annoying with all the random things on my path and multiple terminal and shells installed over the years (got the windows CMD, git bash with mingw, msys2, and cygwin).